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| (R) ICL7126 Data Sheet October 25, 2004 FN3084.5 3 1/2 Digit, Low Power, Single Chip A/D Converter The ICL7126 is a high performance, very low power 31/2-digit, A/D converter. All the necessary active devices are contained on a single CMOS IC, including seven segment decoders, display drivers, reference, and clock. The ICL7126 is designed to interface with a liquid crystal display (LCD) and includes a backplane drive. The supply current of 100A is ideally suited for 9V battery operation. The ICL7126 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10V, zero drift of less than 1V/oC, input bias current of 10pA maximum, and rollover error of less than one count. The versatility of true differential input and reference is useful in all systems, but gives the designer an uncommon advantage when measuring load cells, strain gauges and other bridge-type transducers. And finally the true economy of single power operation allows a high performance panel meter or multi-meter to be built with the addition of only 10 passive components and a display. The ICL7126 can be used as a plug-in replacement for the ICL7106 in a wide variety of applications, changing only the passive components. Features * 8,000 Hours Typical 9V Battery Life * Guaranteed Zero Reading for 0V Input on All Scales * True Polarity at Zero for Precise Null Detection * 1pA Typical Input Current * True Differential Input and Reference * Direct LCD Display Drive - No External Components Required * Pin Compatible With the ICL7106 * Low Noise - Less Than 15VP-P * On-Chip Clock and Reference * Low Power Dissipation Guaranteed Less Than 1mW * No Additional Active Circuits Required * Pb-Free Available (RoHS Compliant) Pinout ICL7126 (PDIP) TOP VIEW V+ D1 C1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 OSC 1 39 OSC 2 38 OSC 3 37 TEST 36 REF HI 35 REF LO 34 CREF+ 33 CREF32 COMMON 31 IN HI 30 IN LO 29 A-Z 28 BUFF 27 INT 26 V25 G2 (10s) 24 C3 23 A3 22 G3 21 BP/GND (100s) Ordering Information TEMP. RANGE PART NUMBER (C) ICL7126CPL ICL7126CPLZ (Note 1) NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. (10s) PACKAGE 40 Ld PDIP PKG. DWG. # E40.6 B1 (1s) A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 (100s) B3 F3 E3 (1000) AB4 POL (MINUS) 0 to 70 0 to 70 40 Ld PDIP E40.6 (Pb-free) (Note 2) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7126 Absolute Maximum Ratings Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to VClock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+ Thermal Information Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC NOTE: Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to 100A. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Zero Input Reading Ratiometric Reading Rollover Error TA = 25oC, VREF = 100mV, fCLOCK = 48kHz (Notes 1, 3) TEST CONDITIONS MIN TYP MAX UNITS VIN = 0.0V, Full Scale = 200mV VlN = VREF , VREF = 100mV -VIN = +VlN 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) VCM = 1V, VIN = 0V, Full Scale = 200mV (Note 5) VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5) VlN = 0V (Note 5) VlN = 0V, 0oC To 70oC (Note 5) VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/xoC) (Note 5) VIN = 0V (Does Not Include COMMON Current) 25k Between Common and Positive Supply (With Respect to + Supply) 25k Between Common and Positive Supply (With Respect to + Supply) (Note 5) V+ = to V- = 9V (Note 4) vs Clock Frequency -000.0 999 - 000.0 999/100 0 0.2 +000.0 1000 1 Digital Reading Digital Reading Counts Linearity Common Mode Rejection Ratio Noise Leakage Current Input Zero Reading Drift Scale Factor Temperature Coefficient V+ Supply Current COMMON Pin Analog Common Voltage Temperature Coefficient of Analog Common Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage Power Dissipation Capacitance 2.4 4 - 0.2 50 15 1 0.2 1 70 3.0 80 5.5 40 1 10 1 5 100 3.2 6 - Counts V/V V pA V/oC ppm/oC A V ppm/oC V pF NOTES: 3. Unless otherwise noted, specifications are tested using the circuit of Figure 1. 4. Back plane drive is in phase with segment drive for `off' segment, 180 degrees out of phase for `on' segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 2 FN3084.5 ICL7126 Typical Application Schematics C3 R1 R5 240k 1M C5 R3 180k R4 10k C1 0.1F 0.01 C2 R2 0.22F 0.047F 180k C4 50pF 750 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 ICL7126 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 1. ICL7126 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE SET REF = 100.0mV R1 R5 240k 1M C5 R3 180k 0.33F 180k C1 0.1F 0.15F C4 50pF 0.01 R4 10k C2 R2 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 ICL7126 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 2. ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/S 3 BP 21 - + + IN - 9V C3 BP 21 + + IN - 9V DISPLAY C1 = 0.1F C2 = 0.22F C3 = 0.047F C4 = 50pF C5 = 0.01F R1 = 240k R2 = 180k R3 = 180k R4 = 10k R5 = 1M DISPLAY C1 = 0.1F C2 = 0.33F C3 = 0.5F C4 = 50pF C5 = 0.01F R1 = 240k R2 = 180k R3 = 180k R4 = 10k R5 = 1M FN3084.5 ICL7126 Typical Application Schematics (Continued) + IN R1 240k R5 1M C5 R3 180k 0.22F C1 0.1F 0.047F 180k C4 50pF 0.01 R4 10k C2 R2 C3 750 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 ICL7126 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 3. CLOCK FREQUENCY 48kHz, 3 READINGS/S 4 BP 21 DISPLAY + - 9V C1 = 0.1F C2 = 0.22F C3 = 0.047F C4 = 50pF C5 = 0.01F R1 = 240k R2 = 180k R3 = 180k R4 = 10k R5 = 1M FN3084.5 ICL7126 Design Information Summary Sheet * OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50k fOSC (Typ) = 48kHz * OSCILLATOR PERIOD tOSC = RC/0.45 * INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC /4 * INTEGRATION PERIOD tINT = 1000 x (4/fOSC) * 60/50Hz REJECTION CRITERION tINT /t60Hz or tlNT /t50Hz = Integer * OPTIMUM INTEGRATION CURRENT IINT = 4A * FULL-SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) = 200mV or 2V * INTEGRATE RESISTOR V INFS R INT = ---------------I INT * DISPLAY COUNT V IN COUNT = 1000 x -------------V REF * CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms * COMMON MODE INPUT VOLTAGE (V- + 1V) < VlN < (V+ - 0.5V) * AUTO-ZERO CAPACITOR 0.01F < CAZ < 1F * REFERENCE CAPACITOR 0.1F < CREF < 1F * VCOM Biased between V+ and V* VCOM V+ - 2.8V Regulation lost when V+ to V- < 6.8V; If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off * ICL7126 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VTEST V+ - 4.5V * ICL7126 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude * INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = ------------------------------V INT * INTEGRATOR OUTPUT VOLTAGE SWING ( t INT ) ( I INT ) V INT = ------------------------------C INT * VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 5 FN3084.5 ICL7126 Detailed Description Analog Section Figure 4 shows the Functional Diagram of the Analog Section for the ICL7126. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). De-integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator to output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically, the digital reading displayed is: VIN Display Count = 1000 -------------- . VREF Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10V. Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.5V of either supply without loss of linearity. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. CREF RINT CREF+ V+ 34 REF HI 36 A-Z 1A 31 IN HI INT DEDE+ INPUT HIGH 6.2V A-Z REF LO 35 A-Z CREF33 BUFFER V+ 28 1 29 INTEGRATOR + CAZ A-Z CINT INT 27 + - - + 2.8V TO DIGITAL SECTION A-Z N 32 COMMON A-Z AND DE() 30 IN LO INT 26 VINPUT LOW DE+ DE+ COMPARATOR - FIGURE 4. ANALOG SECTION OF ICL7126 6 FN3084.5 ICL7126 V+ V+ V+ REF HI REF LO 6.8V ZENER IZ V+ 27k 200k ICL7126 ICL7126 REF HI REF LO COMMON VICL8069 1.2V REFERENCE FIGURE 5A. FIGURE 5. FIGURE 5B. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N channel FET that can sink approximately 3mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 1A of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. Analog COMMON This pin is included primarily to set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (<6.8V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15), and a temperature coefficient typically less than 80ppm/oC. The limitations of the on-chip reference should also be recognized, however. The reference Temperature Coefficient (TC), can cause some degradation in performance. Temperature changes of 2oC to 8oC, typical for instruments, can give a scale factor error of a count or more. Also the common voltage will have a poor voltage coefficient when the total supply voltage is less than that which will cause the zener to regulate (<7V). These problems are eliminated if an external reference is used, as shown in Figure 5. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog 7 FN3084.5 ICL7126 V+ V+ V+ 1M TO LCD DECIMAL POINT BP ICL7126 BP TEST 21 ICL7126 DECIMAL POINT SELECT TO LCD DECIMAL POINTS TEST 37 TO LCD BACKPLANE V+ = DP ON GND = DP OFF CD4030 GND FIGURE 6. SIMPLE INVERTER FOR FIXED DECIMAL POINT FIGURE 7. EXCLUSIVE `OR' GATE FOR DECIMAL POINT DRIVE TEST The TEST pin serves two functions. It is coupled to the internally generated digital supply through a 500 resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 6 and 7 show such an application. No more than a 1mA load should be applied. The second function is a "lamp test". When TEST is pulled high (to V+) all segments will be turned on and the display should read "-1888". The TEST pin will sink about 10mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave) and may burn the LCD display if left in this mode for several minutes. to 3000 counts). For signals less than full-scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/sec.) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). Digital Section Figure 8 shows the digital section for the ICL7126. An internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. The polarity indication is "ON" for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. System Timing Figure 9 shows the clocking arrangement used in the ICL7126. Two basic clocking arrangements can be used: Figure 9A, an external oscillator connected to pin 40. Figure 9B, an R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 8 FN3084.5 ICL7126 a a f g b e d c b BACKPLANE 21 LCD PHASE DRIVER TYPICAL SEGMENT OUTPUT V+ 0.5mA SEGMENT OUTPUT 2mA 1000's COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 7 SEGMENT DECODE 7 SEGMENT DECODE 7 SEGMENT DECODE /200 LATCH 100's COUNTER 10's COUNTER 1's COUNTER 35 V+ 6.2V 500 INTERNAL DIGITAL GROUND TEST VTH = 1V 37 THREE INVERTERS. ONE INVERTER SHOWN FOR CLARITY. CLOCK /4 LOGIC CONTROL 26 40 OSC 1 OSC 2 39 OSC 3 38 1 HLDR V- FIGURE 8. DIGITAL SECTION INTERNAL TO PART INTERNAL TO PART /4 40 39 38 CLOCK /4 40 39 R 38 C CLOCK TEST ICL7126 FIGURE 9A. EXTERNAL SIGNAL FIGURE 9. CLOCK CIRCUITS FIGURE 9B. RC OSCILLATOR 9 FN3084.5 ICL7126 Component Value Selection Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 6A of quiescent current. They can supply ~1A of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full-scale, 1.8M is near optimum and similarly a 180k for a 200mV scale. VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full-scale reading when the voltage from the transducer is 0.682V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor 330k. This makes the system slightly quieter and also avoids a divider network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not saturate the integrator swing (approximately. 0.3V from either supply). When the analog COMMON is used as a reference, a nominal 2V full-scale integrator swing is fine. For three readings/second (48kHz clock) nominal values for ClNT are 0.047F, for 1/s (16kHz) 0.15F. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. The integrating capacitor should have a low dielectric absorption to prevent roll-over errors. While other types may be adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. At three readings/sec, a 750 resistor should be placed in series with the integrating capacitor, to compensate for comparator delay. Typical Applications The ICL7126 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Intersil Corporation. Application Notes NOTE # AN016 AN017 AN018 AN023 AN032 AN046 AN052 DESCRIPTION "Selecting A/D Converters" "The Integrating A/D Converter" "Do's and Don'ts of Applying A/D Converters" "Low Cost Digital Panel Meter Designs" "Understanding the Auto-Zero and Common Mode Performance of the ICL7136/7/9 Family" "Building a Battery-Operated Auto Ranging DVM with the ICL7106" "Tips for Using Single-Chip 31/2 Digit A/D Converters" Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full-scale where noise is very important, a 0.32F capacitor is recommended. On the 2V scale, a 0.33F capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor A 0.1F capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1F will hold the roll-over error to 0.5 count in this instance. Oscillator Components For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximation equation 0.45 f ---------- * For 48kHz clock (3 readings/sec), R = 180k RC Reference Voltage The analog input required to generate full-scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, 10 FN3084.5 ICL7126 Typical Applications OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP/GND 21 TO BACKPLANE TO DISPLAY 750k 0.047F 0.01F 0.33F 180k 10k 0.1F 1M + IN 220k 50pF SET VREF = 100mV 180k OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 200k 27k 0.1F 1M 0.01F 0.33F 180k + IN V+ 50pF 20k SET VREF = 100mV 560k + 9V SET VREF = 1.000V 240k 1M 0.01F IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP/GND 21 - Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). FIGURE 10. ICL7126 USING THE INTERNAL REFERENCE OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP/GND 21 180k 50pF 250k 0.1F 0.22F 1.8M 750 0.047F TO DISPLAY TO BACK PLANE 3 reading/s. For 1 reading/sec., delete 750 resistor, change CINT, ROSC to values of Figure 11. FIGURE 12. RECOMMENDED COMPONENT VALUES FOR 2.0V FULL SCALE 11 V+ + IN 0.15F V- TO DISPLAY IN LO is tied to COMMON, thus establishing the correct common mode voltage. COMMON acts as a pre-regulator for the reference. Values shown are for 1 reading/sec. FIGURE 11. ICL7126 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V 100k SET VREF = 100mV +5V 1k 10k 15k 0.1F 1.2V (ICL8069) 1M 0.01F 0.47F 47k + IN 100pF - - - V - 26 G2 25 C3 24 A3 23 G3 22 BP/GND 21 0.22F TO DISPLAY Since low TC zeners have breakdown voltages ~6.8V, diode must be placed across the total supply (10V). As in the case of Figure 12, IN LO may be tied to COMMON. FIGURE 13. ICL7126 WITH ZENER DIODE REFERENCE FN3084.5 ICL7126 Typical Applications OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO BACK PLANE TO DISPLAY 0.01F 0.33F 180k 20k 100k 0.1F 1.2V (ICL8069) 1M + IN 27k +5V 50pF (Continued) V+ OSC 1 40 OSC 2 39 SET VREF = 100mV OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO BACK PLANE TO DISPLAY 0.33F RINT 0.1F 50pF - An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. indicates values depend on clock frequency. FIGURE 14. ICL7126 OPERATED FROM SINGLE +5V SUPPLY The resistor values within the bridge are determined by the desired sensitivity. indicates values depend on clock frequency. FIGURE 15. ICL7126 MEASURING RATIOMETRIC VALUES OF QUAD LOAD CELL OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21 0.1F 50pF SCALE FACTOR ADJUST 100k 100k 1M 200k 470k 0.01F 0.33F 390k ZERO ADJUST + SILICON NPN MPS 3704 OR SIMILAR 9V TO DISPLAY TO BACKPLANE A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 16. ICL7126 USED AS A DIGITAL CENTIGRADE THERMOMETER 12 FN3084.5 ICL7126 Typical Applications (Continued) V+ 1 V+ 2 D1 TO LOGIC VCC 3 C1 4 B1 5 A1 6 F1 7 G1 8 E1 9 D2 10 C2 11 B2 12 A2 13 F2 14 E2 O /RANGE 15 D3 16 B3 17 F3 18 E3 U /RANGE 19 AB4 20 POL OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 TO CREF 34 LOGIC GND CREF 33 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 BP 21 V- COMMON 32 CD4023 OR 74C10 CD4077 FIGURE 17. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7126 OUTPUTS TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21 TO BACKPLANE TO DISPLAY 0.047F 180k 750 10F 0.22F + 10k 0.1F 1F 4.3k 0.22F 9V 100pF (FOR OPTIMUM BANDWIDTH) 10k 1F 10k 1F 220k 470k 2.2M 1N914 50pF 180k 10F SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) 5F ICL7611 + 100k - AC IN Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 18. AC TO DC CONVERTER WITH ICL7126 13 - FN3084.5 ICL7126 Die Characteristics DIE DIMENSIONS: 127 mils x 149 mils METALLIZATION: Type: Al Thickness: 10kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 PASSIVATION: Type: PSG Nitride Thickness: 15kA 3kA Metallization Mask Layout ICL7126 E2 (14) F2 (13) A2 (12) B2 (11) C2 (10) D2 (9) E1 (8) G1 (7) F1 (6) A1 (5) D3 (15) B3 (16) F3 (17) E3 (18) AB4 (19) POL (20) BP/GND (21) (4) B1 (3) C1 (2) D1 (1) V+ (40) OSC 1 G3 (22) A3 (23) C3 (24) G2 (25) (38) OSC 3 (37) TEST (39) OSC 2 V- (26) (27) INT (28) BUFF (29) A/Z (30) IN LO (31) IN HI (32) COMM (33) (34) (35) LO REF (36) HI REF CREF- CREF+ 14 FN3084.5 ICL7126 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E40.6 (JEDEC MS-011-AC ISSUE B) 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 50.3 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 53.2 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.125 0.014 0.030 0.008 1.980 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 2.095 0.625 0.580 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.600 BSC 0.115 40 0.700 0.200 2.54 BSC 15.24 BSC 2.93 40 17.78 5.08 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN3084.5 |
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